Parent Partition Virtual Processors Test

A virtual processor is a single logical processor that is exposed to a partition by the hypervisor.  Virtual processors can be mapped to any of the available logical processors in the physical computer and are scheduled by the hypervisor to allow you to have more virtual processors than you have logical processors.

This test monitors how well the parent partition uses the virtual processors assigned to it.

Target of the test : A Hyper-V / Hyper-V VDI server

Agent executing the test : An internal agent

Output of the test : One set of results for the every virtual processor assigned to the root partition of the Hyper-V host monitored

Configurable parameters for the test
  1. Test period - How often should the test be executed
  2. Host - The host for which the test is to be configured.
Measurements reported by the test
Measurement Description Measurement Unit Interpretation

Parent partition run time

Indicates the percentage of time spent by this virtual processor (VP) in guest code. For the Summary descriptor, the value of this measure is the total percentage across all VPs.

Percent

Comparing the value of this measure across VPs will accurately indicate which VP is being actively used by the guests.

Hypervisor runtime

Indicates the percentage of time spent by the virtual processor in hypervisor code. For the Summary descriptor, the value of this measure is the total percentage across all VPs.

Percent

Comparing the value of this measure across VPs will accurately indicate which VP is being actively used by the hypervisor.

Parent partition CPU utilization

Indicates the total percentage of time this VP was in use. For the Summary descriptor, this is the average percentage of time for which all VPs were in use.

Percent

This is typically the sum of the Parent partition runtime and Hypervisor runtime measures. Comparing the value of this measure across VPs will reveal the VP that is being utilized excessively.

Control register accesses

Indicates the number of CPU Control Register accesses per second. For the Summary descriptor, this is rate of CPU control register accesses across all VPs.

Accesses/Sec

Control registers are used to set up address mapping, privilege mode, etc.

CPUID instructions

Indicates the number of CPUID instructions calls per second. For the Summary descriptor, this is rate of CPUID instructions across all VPs.

Instructions/Sec

The CPUID instruction is used to retrieve information on the local CPU’s capabilities. Typically, CPUID is only called when the OS / Application first start. Therefore, this value is likely to be 0 most of the time.

Emulated instructions

Indicates the number of emulated instructions completed per second. For the Summary descriptor, this is rate of emulated instructions completed across all VPs.

Instructions/Sec

Some instructions require emulation to complete in the Hypervisor. One such example is APIC access.

HLT instructions

Indicates the number of CPU halts per second on the VP. For the Summary descriptor, this is the total number of CPU halts (per second) across all VPs.

Instructions/Sec

A HLT will cause the hypervisor scheduler to de-schedule the current VP and move to the next VP in the runlist.

Hypercalls

 

Indicates the number of hypercalls made by guest code on the VP per second. For the Summary descriptor, this is the total number of hypercalls made on all VPs per second.

Hypercalls/Sec

Hypercalls are one form of enlightenment.  Guest OS’s use the enlightenments to more efficiently use the system via the hypervisor. TLB flush is an example hypercall. If this value is zero, it is an indication that Integration Components are not installed.  New OS’s like WS08 can use hypercalls without enlightened drivers. So, hypercalls are only a prerequisite and not a guarantee for not having Integration Components installed.

IO instructions

Indicates the number of CPU in / out instructions executed per second. For the Summary descriptor, this is total number of IO instructions executed on all VPs per second.

Instructions/Sec

Many older or low bandwidth devices use “programmed I/O” via in / out instructions.

Large page TLB fills

Indicates the number of Large Page TLB fills / second. For the Summary descriptor, this is rate of large page TLB fills across all VPs per second.

Fills/Sec

There are two types of TLB entries (and some three).  Small TLB which generally means a 4K page and large Page which generally means 2MB.  There are fewer Large TLB entries on the order of 8 – 32.

A non-zero value for this measures indicates that the root partition is using large pages.

MSR accesses

Indicates the number of Machine Specific Register (MSR) instruction calls per second.For the Summary descriptor, this is total number of MSR instruction calls made on all VPs per second.

Accesses/Sec

There are many types of MSRs such as C-state config, Synthetic Interrupt (Synic) Timers, and control functions such as shutdown.

MWAIT instructions

Indicates the number of MWAIT instructions per second. For the Summary descriptor, this is the total number of MWAIT instructions executed on all VPs per second.

Instructions/Sec

The mwait (monitored wait) instruction instructs the processor to enter a wait state in which the processor is instructed to monitor the address range between a and b and wait for an event or a store to that address range.

Page fault intercepts

Indicates the number of page faults per second. For the Summary descriptor, this is the total number of page faults on all VPs per second.

Intercepts/Sec

Whenever guest code accesses a page not in the CPU TLB a page fault will occur. This counter is closely correlated with the Large Page TLB Fills measure.

Small page TLB fills

Indicates the number of Small Page TLB fills / second. For the Summary descriptor, this is rate of small page TLB fills across all VPs.

Fills/Sec

There are two types of TLB entries (and some three).  Small TLB which generally means a 4K page and large Page which generally means 2MB.  There are fewer Large TLB entries on the order of 64 – 1024+. 

Total intercepts

Indicates the rate of hypervisor intercept messages. For the Summary descriptor, this is rate at which intercepts occurred across all VPs per second.

Intercepts/Sec

Whenever a guest VP needs to exit its current mode of running for servicing in the hypervisor, this is called an intercept.  Some common causes of intercepts are resolving Guest Physical Address (GPA) to Server Physical Address (SPA) translations, privileged instructions like hlt / cupid / in / out, and the end of the VP’s scheduled time slice.

CPU ready time

Indicates the time duration during which this VP was ready to execute the requests to the logical processor but was not able to because of processor contention.

Milliseconds

The value of this measure should typically be low. The more time a VP spends waiting to run, the more lag time there is in responsiveness within the VP.